GigE Packet Handling FPGA

Working closely with our client, FBM developed the FPGA section of a layer-2 network communications protocol tester. The Xilinx SpartanIIE design consisted of a duplex Ethernet Gigabit interface and two line-rate duplex 10/100 Ethernet interfaces linking the product and the unit under test. The gigabit MMI was run at 125MHz, the 10/100 MMI at 2.5MHz/25MHz and a 100MHz SDRAM and memory arbitor was also required.

Video Stream Mixing

This design combined two disparate media streams under control of the end-user. The solution used standard video decoder/display driver IC's, video frame buffers as DPRAM and a CPLD for the multiplexing tasks. FBM wrote the CPLD code and the embedded code for the PIC processor to control and synchronise all these devices via I2C, depending on user input via mechanical controls and frame-rate/format variations.